FIG. 1 shows an example of a conventional direct-current converter (Japanese Patent Laid-Open Publication No. 2000-92829). The direct-current converter shown in FIG. 1 has a system called “active clamp”. To a direct-current power supply Vin, a main switch Q1 formed of a MOSFET (hereinafter, referred to as an FET) and the like is connected through a primary winding P1 (winding number: n1) of a transformer T. To both ends of the primary winding P1, a series circuit composed of an auxiliary switch Q2 formed of a MOSFET (hereinafter, referred to as an FET) and the like and composed of a snubber capacitor C2 is connected. The main switch Q1 and the auxiliary switch Q2 are configured to be alternately switched on/off by PWM control of a control circuit 111.
Moreover, the primary winding P1 of the transformer T and a secondary winding S1 of the transformer T are wound so as to generate a common mode voltage to each other. To the secondary winding S1 (winding number: n2) of the transformer T, a rectifying/smoothing circuit composed of diodes D10 and D11, a reactor L10 and a capacitor C10 is connected. The rectifying/smoothing circuit rectifies and smoothes a voltage (a pulse voltage of which ON/OFF is controlled) induced by the secondary winding S1 of the transformer T, and outputs a direct-current output to a load 30.
Based on an output voltage of the load 30, the control circuit 111 generates a control signal formed of a pulse for controlling the ON/OFF of the main switch Q1, and controls a duty ratio of the control signal so that the output voltage becomes a predetermined voltage. Moreover, the direct-current converter includes an inverter 112, a bottom detection circuit 113, a first delay circuit 114, a second delay circuit 115, a low-side driver 116, and a high-side driver 117.
The inverter 112 inverts a Q1 control signal Q1c for the main switch Q1 from the control circuit 111, and outputs the inverted Q1 control signal Q1c to the second delay circuit 115. The bottom detection circuit 113 detects the minimum voltage (hereinafter, referred to as a bottom detection signal Btm) of the main switch Q1 after the auxiliary switch Q2 is switched off. The first delay circuit 114 generates a Q1 gate signal Q1g in which rising timing of a Q1 control signal Q1c from the control circuit 111 is delayed to rising timing of the bottom detection signal Btm from the bottom detection circuit 113, and outputs the generated Q1 gate signal Q1g to the low-side driver 116. The low-side driver 116 applies the Q1 gate signal Q1g from the first delay circuit 114 to a gate of the main switch Q1, and drives the main switch Q1. The second delay circuit 115 generates a Q2 gate signal Q2g in which rising timing of the Q2 control signal Q2c for the auxiliary switch Q2, which is inverted by the inverter 112, is delayed by a predetermined time, and outputs the generated Q2 gate signal Q2g to the high-side driver 117. The high-side driver 117 applies the Q2 gate signal Q2g from the second delay circuit 115 to a gate of the auxiliary switch Q2, and drives the auxiliary switch Q2.
Next, operations of the direct-current converter thus configured will be described while referring to a timing chart shown in FIG. 2. In FIG. 2, a voltage Q1v between both ends of the main switch Q1 is shown.
First, when the Q1 control signal Q1c from the control circuit 111 rises to a H level at a time t31, the Q2 control signal Q2c falls to a L level. Accordingly, the Q2 gate signal Q2g falls to the L level, and therefore, the auxiliary switch Q2 is switched off. Moreover, the bottom detection signal Btm rises to the H level at the time t31.
Then, when the auxiliary switch Q2 is switched off, the voltage Q1v of the main switch Q1 is decreased. At a time t32, the minimum value (bottom) of the voltage Q1v is detected by the bottom detection circuit 113. At this time, the bottom detection signal Btm from the bottom detection circuit 113 falls to the L level.
Then, the Q1 gate signal Q1g which rises to the H level at falling timing (time 32) of the bottom detection signal Btm from the bottom detection circuit 113 is generated by the first delay circuit 114, and the Q1 gate signal Q1g is applied to the gate of the main switch Q1 through the low-side driver 116. Accordingly, the main switch Q1 is switched on. Specifically, a bottom-voltage switch or zero-voltage switch of the main switch Q1 can be achieved.
When the main switch Q1 is switched on, a current flows to the main switch Q1 from the direct-current power supply Vin through the primary winding P1 of the transformer T. At this time, the current flows through a cycle of the constituents S1, D10, L10, C10 and S1.
Next, when the main switch Q1 is switched off by the Q1 control signal Q1c at a time t33, a parasitic capacitor (not shown) owned by the main switch Q1 is charged with energy stored in the primary winding P1 of the transformer T and a leakage inductance between the primary and secondary windings of the transformer T, a voltage resonance is formed, and the voltage Q1v of the main switch Q1 rises during a period from the time t33 to a time t34. Moreover, a current flows through a cycle of the constituents L10, C10, D11 and L10, and supplied to a load R30.
Then, when the auxiliary switch Q2 is switched on by the Q2 gate signal Q2g at the time t34, the energy stored in the primary winding P1 of the transformer T is supplied to the capacitor C2, and the capacitor C2 is charged therewith. Next, the energy stored in the capacitor C2 flows through a cycle of the constituents C2, Q2, P1 and C2.
Note that, as a document of a related art of the conventional direct-current converter, for example, Japanese Patent Laid-Open Publication No. H7-203688 (published in 1995) is mentioned.